The improved performance of a GaAs MESFET (Metal Semiconductor FET) can be achieved by the high cutoff frequency, the lower parasitic resistance and the reduced noise coefficient.
For these purposes, there have been employed the various methods such as the adoration of the short gate length, a recessed gate structure, an n+ source/drain contact area, or the buffer layer in the device.
FIG. 1 shows a sectional view of GaAs MESFET having a recessed gate according to the conventional art.
The device includes an active area 3 formed over a GaAs substrate 1 through the interposed buffer layer 2 therebetween, a source electrode 5 and a drain electrode 6 which are spaced apart from each other, a recessed channel in the active area 3 and between the source electrode 5 and the drain electrode 6, and a gate electrode 4 on the recessed channel part.
Although the MESFET having the recessed gate can be fabricated through the simple procedures, the device has the drawbacks of the lower breakdown voltage between the source and the drain, making it improper to use as a power element, and the worse microwave performance due to the electric field accumulation between the gate electrode 4 and the drain electrode 6.
So as to solve the above drawbacks, M. M. Macksey, et al, has proposed the manufacturing method of the GaAs FET having the double recessed channel, which will be explained below, with reference to FIGS. 2A to 2G.
As shown in FIG. 2A, after a source pole and a drain pole are formed by depositing metal on a GaAs semiconductor layer 15 having stacks of a substrate 11, a buffer layer 12, an n type region 13 and an n+ type region 14, and on the stacks are sequentially deposited a photoresist film for leveling or a planarizing layer 16, a PMMA layer 17, a layer of Ge 18 and another PMMA layer or an imaging layer 19, leading to the multilayer structure.
By use of the electron-beam lithography technique, the imaging layer 19 is patterned to form a gate electrode pattern as shown in FIG. 2B.
Next, referring to FIG. 2C, the imaging layer having the gate pattern therein acts as the etch mask during Reactive Ion Etch (RIE) process using O.sub.2 for selectively etching a layer of Ge 18, the PMMA layer 17 and the planarizing layer 16, whereby the top layer of PMMA layer or imaging layer is vanished during RIE process using O.sub.2 associated with the PMMA layer 17 and the planarizing layer 16.
The etching of a layer of Ge 18, PMMA layer 17 and planarizing layer 16 allows the n+ type region 14 to partly expose and then the exposed area is further wet etched in a constant depth to form a first recess or gate recess, as shown in FIG. 2D.
A layer of Ge 18 and the planarizing layer 16 underneath the PMMA layer 17 are then removed using the developer, thereby leaving partly under cut structure as shown in FIG. 2E.
The n+ type region 14 and the n type region 13 are wet etched to form a second recess or a wide recess, which is shown in FIG. 2F. Next, as shown in FIG. 2G, after deposition of metal on the GaAs semiconductor layer 15, the layers of germanium 18, PMMA 17 and image 19 are totally removed using lift-off process, and a source electrode 21 and a drain electrode 22 are formed by depositing a metal on the wide recessed GaAs semiconductor layer 15. Thus, the fabrication of the FET is completed. The n+ type ledge channel structure by the conventional art makes the wide recess width narrower, so that the gate electrode 20 is positioned near the n+ type region 14. Thus, the transfer gain increases with the decrease in the parasitic resistance Rs between the source electrode and the gate electrode, but the gain is rather lower because of the increased feedback capacitance Cdg between the gate electrode and the drain electrode. Also, the gate breakdown voltage tends to be lower.
Meanwhile, the wider width of the wide recess causes to increase the parasitic resistance between the source electrode and the gate electrode, which results in the lower gain. Thus, it is necessary to defining the width of the wide recess so as to take the balanced values of the transfer gain and the breakdown voltage.
Another problem in the prior art is that there must be optimally formed the width of the wide recess and the width/depth of the gate recess at the etch processes in twice for forming the gate recess and the wide recess.